North America: October 1 & 2, 2019 at Fairmont San Jose (USA)
EMEA: November 12 & 13, 2019 at World Forum, The Hague (Netherlands)
Asia: December 3 & 4, 2019 at National Convention Center, Beijing (China)
Demonstrate VARON and VSTAR consisting of on-chip verification IP developed in-house and proprietary GUI software.
- Present the product’s system configuration and advantages, followed by design flow demonstration using GUI software.
- VARON software displays charts for data transfer amount, bus transactions, and latency distribution. The demo DUT consisting of 8 bus masters and 2 bus slaves is connected to software verification IP via DPI-C and operated by software simulator.
- VSTAR software displays the entire signals sequences with auto-detected errors and outputs VCD for waveform observation. The demo DUT and hardware verification IP are implemented into Xilinx UltraScale+ FPGA for real operation.
Present functional safety support for Xilinx FPGAs.
- Utilization of “Xilinx Safety Manual” in safety analysis
- FPGA development method using Xilinx Safety Lounge utility