FPGA debugging challenges

The following problems may be encountered when debugging FPGA circuit failures using conventional debugging tools.

  • When a problem occurs, it is not possible to immediately specify the timing of the problem.

It takes several trials and errors to find the appropriate trigger conditions for unexpected failures. In some cases, re-synthesis is required, and it may take a considerable amount of time to identify the timing of the failure.

  • It takes time to debug while reviewing the system level operation.

A large amount of BRAMs is required to acquire a long-time signal waveform at the system level, but depending on the number of BRAMs available, it may be possible to acquire only a waveform in a very narrow time range. Therefore, the trigger condition for identifying the timing of failure occurrence becomes complicated.

VSTAR solution

VSTAR is an FPGA debugging tool with automatic failure analysis that solves these problems.

  • Even if a system-level failure occurs coincidentally after the FPGA has been running for several days, the operating status at the time of the failure is captured and user can immediately start debugging.

By automatically extracting the rules from sequences of signal changes and monitoring the FPGA operation based on the rules, VSTAR automatically generates the internal trigger when a problem occurs.

No user setting of trigger conditions is required

  • Acquires system-level long-term operation and detailed signal waveforms at the same time, and user can debug while referring to system-level charts and detailed signal waveforms at the same time.

Captures a range of thousands to tens of thousands times longer than before on the time axis by only recording signal change points for system level operation and greatly improves the use efficiency of BRAM.

VSTAR configuration

VSTAR consists of an on-chip verification IP (VSTAR IP) and a proprietary GUI.

Offers automatic implementation of verification IP (VSTAR IP) with GUI, and supports selection of probe signal, change of settings such as buffer size, automatic integration into user circuit, and automatic wiring. Since the JTAG terminal is used, no additional terminal is required. The JTAG terminal is shared with Vivado.

Application example 1 – State machine, timeout error monitoring

VSTAR automatically generates the rule by the sequence of signal changes and the timing intervals, and detects unusual state transitions and timing intervals.

  • State machine monitoring: VSTAR detects unusual state transitions

  • Time-out error detection: VSTAR detects the state where there is no response to the request within a certain time on the bus, etc.

  • Hang-up detection: VSTAR detects the hang state of the circuit by the capability to detect the state where an event does not occur for a certain period of time.

Application example 2 – System level debugging including CPU operation

This is an example of displaying long-term system-level operation and detailed signal waveforms at the same time for debugging a system where software is executed by a CPU to control the entire system. By probing the value of the CPU address bus and the signal indicating the operating status of the IPs connected to the bus, the operating sequence of the entire system including the software can be verified.

  • Block diagram of a system consisting of 4 bus masters

Master 0 is the CPU, which controls the entire system. Master 1, 2 and 3 are DMA, USB IP, etc., and starts transfer under the control of the CPU.

  • Example of system operation timing and probe signal

The system repeats the same operation with a cycle of about 27,000 clocks. The CPU (Master 0) accesses the registers and allows Master 1, 2 and 3 to start data transfer. To check the operating status of the CPU, adds a probe to detect the value of 0x0800, 0x0E00, 0x1200 and 0x1C00 among the address values ​​output to the bus and generate an event, and also probes each enable signal that controls the transfer start of Master 1, 2 and 3.

  • Actual operation and events detected by the probe

Events indicating the value matches occur on the CPU address bus, and events indicating the rising edges of the enable signal for Master 1, 2 and 3 occur in the order shown below.

  • VSTAR Event Transition Chart

VSTAR displays system-level operation for a period of 100,000 clocks or more for this example. Overall, it captures behavior over millions of cycles and displays the perod of time that cannot be handled by conventional waveform display tools.

  • Waveform example

Displays the detailed signal waveform near the error detected by VSTAR to GTKWave.

Application example 3 – Debugging pixel data missing / duplicate in image processing circuits

This is an example of applying VSTAR’s rule extraction of signal states transitions to the detection of data change regularity. Due to a defect in the image processing pipeline circuit, pixel data omission and duplication may occur. Even if the number of pixel data in one line (in one frame) is correct and there is an error only in the pixel data, VSTAR can analyzes it.

  • Use VSTAR to probe the input / output data of each module that makes up the image processing pipeline circuit.

  • Enter periodic image data for debugging to make it easier for VSTAR to extract the rules. In this example, the image data has periodic vertical lines.

  • If pixel data is missing or duplicated inside the image processing circuit, the time when the vertical line part of the pixel data is output will shift. As a result, the timing interval of the event that detects the data change in the vertical line part is different, and VSTAR can detect it as an error.

Application example 4

Blog posted for an example of analyzing a defect in an image processing circuit using VSTAR.