Vtech introduces another VSTAR demo with video image processing.  The image rotating algorithm is mapped to a Xilinx Kintex-7 FPGA K705 development board with a 300 MHz AXI stream and 200 MHz AXI bus.

Figure 1: VSTAR image processing demo block diagram


Three sets of bus probes are chosen and VSTAR automatically generates rules based on the selected probes. VSTAR then automatically detects error conditions and displays the faults. Manual override is available for the rules.

A special hardware “error injection” switch has been added to manually insert a fault in the design – VSTAR automatically identifies the fault and displays to the user with VCD on GTKWave.

Figure 2: VSTAR image processing demo system configuration


Figure 3: VSTAR image processing demo AXI timing


Figure 4: VSTAR image processing demo probe settings for valid signals of Image Rotator


Figure 5: One of the rules auto-generated by VSTAR for valid signals of Image Rotator


Figure 6: VSTAR image processing demo probe settings for write address of Image Rotator


Figure 7: VSTAR image processing demo probe settings for valid signals of Image DMA Reader


Complex designs are becoming more difficult to debug: where to set probes, compile, place & route, review, reset probes, repeat.  Let VSTAR automatically set the rules and triggers.  Compile less and have more time to debug the root cause.

Schedule a VSTAR FPGA Debug demo to:  vtech_usa_info@vtech-inc.co.jp