Verification Technology, Inc.

VSTAR video processing demo

Vtech introduces another VSTAR demo with video image processing. The image rotating algorithm is mapped to a Xilinx Kintex-7 FPGA K705 development board with a 300 MHz AXI stream and 200 MHz AXI bus.

Figure 1: Block diagram

Three sets of bus probes are chosen. VSTAR captures events (signal states) up to 100,000 times longer than waveform and displays on Event Transition Chart.

VSTAR automatically creates a state machine and internal triggers for each probe group based on Event Transition Chart. Each state machine sequence (rule) is displayed on Event Rules Explorer.

VSTAR then detects mismatches (auto triggers) with the rules and highlights the faults on Event Transition Chart. Manual override is available for the rules and the additional triggers.

A special hardware “error injection” switch has been added to manually insert a fault in the design – VSTAR automatically identifies the fault and displays to the user with VCD on GTKWave.

Figure 2: System configuration

Figure 3: AXI operation timing

Figure 4: Event Transition Chart

Figure 5: Probe settings for valid signals of Image Rotator

Figure 6: One of the rules auto-generated by VSTAR on Event Rules Explorer

Figure 7: Probe settings for write address of Image Rotator

Figure 8: Probe settings for valid signals of Image DMA Reader

Complex designs are becoming more difficult to debug: where to set probes, compile, place & route, review, reset probes, repeat. Let VSTAR automatically set the rules and triggers. Compile less and have more time to debug the root cause.

Schedule a VSTAR FPGA Debug demo to: vtech_usa_info@vtech-inc.co.jp

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VSTAR video processing demo

“Vtech introduces another VSTAR demo with video image processing. The image rotating algorithm is mapped to a Xilinx Kintex-7 FPGA K705 development board with a 300 MHz AXI stream and 200 MHz AXI bus.”