Verification Technology Co., Ltd. (Headquarters: Yokohama Japan, President & CEO: Hideto Takeuchi), which guarantees safety and security of LSI (Large-Scale Integrate circuit) development, announced the release of “VSTAR 2.0 – FPGA debug software with auto-detection of failures” on June 22nd, 2020.
VSTAR 2.0 enables automatic debug even when a problem occurs deep in a continuous FPGA operation for several days. The patent-applied new technology generates rules for the signal state transitions in real time and monitors the state transitions using the auto-extracted rules, while automatically embedding the verification IP into the FPGA. VSTAR 2.0 significantly reduces the user work required to drive to the failure. And, since no additional pins for debugging are required, it can be installed even after the FPGA board is completed. VSTAR 2.0 offers the industry’s only solution that greatly reduces user debugging efforts for complex and high-performance FPGA designs.
Product name: VSTAR 2.0 – FPGA debug software
Product configuration: Verification IP developed in-house and proprietary graphical user interface
Supported FPGA: Xilinx FPGAs
Release date: June 22nd, 2020
- Generates rules for the signal state transitions in real time; monitors the state transitions using the auto-generated rules and automatically identifies operations that are a mismatch with the rules as errors.
- Even if an error occurs after several days of continuous operation, the error and conditions are detected -all without user effort.
- The resulting chart shows the overall operation of the system triggered by the occurrence of an error. And, the detected errors are highlighted.
- The detailed status of signal state transitions at the time of error occurrence are automatically acquired and the waveform is displayed.
- Supports automatic implementation of verification IP into FPGA.
- Since the JTAG terminal is used to connect to the FPGA, no additional terminal is required for debugging.
Company Name: Verification Technology Co., Ltd.
President & CEO: Hideto Takeuchi
Address: 5F, Square BLDG, 2-3-12 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, JAPAN
Veriﬁcation Technology USA, Inc:
Address: 4300 Stevens Creek Blvd., Suite 220, San Jose, CA 95129 USA
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For more information contact
Name: Robert Biczek