Performance Verification Challenges

SoC designs become large-scale and complex with a lot of IPs, and there are many kinds of use cases. Accurate bus performance analysis is becoming more important to bring out the performance. However, the performance verification has the following issues.

"Requires multiple IPs and rich debugging tool"

  • Needs to build the verification environment for each project
  • Critical time spent starting the verification
  • Difficult to standardize the verification method throughout the design process (simulation; emulation; FPGA prototyping; ASIC)

"Takes long time to run simulation due to the large amount of data"

“Necessary to execute actual software on FPGA or ASIC, but there was never an effective solution.”

“It was impossible to grasp the detailed transfer status and verify performance defects occurring on the board using FPGA or ASIC.”


• Offers a single on-chip verification IP and proprietary GUI

  • Short time to the performance verification with the IP flexibly configured and quickly implemented to user design
  • Easy and systematic analysis with rich portfolio of performance charts to visualize bus usage efficiency and responsiveness
  • Tooltip designed for each performance chart to display the detailed data on mouse cursor
  • .csv outputs for regression test with the templates

• Supports AXI3, AXI4, ACE and APB

• Supports simulator, hardware emulator, FPGA, ASIC and ASSP with no discrepancy in the verification results among all platforms, which greatly reduces design backtracking

• Monitors bus at transaction level

  • Enables detailed performance analysis including for FPGA and ASIC
  • Greatly reduces the amount of data to speed chart display

Search for long-latency transactions

Root cause analysis of long latency

• Offers Design Services with VARON

  • Performance verification environment creation
  • Performance optimization and reporting
  • Support for customer proprietary bus protocol

Data Transfer Amount Analysis

In addition to total data transfer amount charts (bar graph and pie chart) and burst length histogram, VARON offers data transfer amount timing charts (by port and stacked view) and transaction timing chart to acquire detailed status at the peak including for FPGA and ASIC.

Total Data Transfer Amount Charts

Time-Series Data Transfer Amount Charts


Latency Analysis

VARON offers latency analysis including for FPGA and ASIC by monitoring AMBA bus at transaction level, which is also suitable for QoS verification while running actual application. It searches for transactions with greater latencies than user targets and highlights on transaction timing chart where transactions are cycle-accurately mapped, and latency histogram.