Performance verification challenges
SoC designs become large-scale and complex with a lot of IPs, and there are many kinds of use cases. Accurate bus performance analysis is becoming more important to bring out the performance.
However, the analysis of bus performance has the following issues.
- There was no dedicated tool for bus performance analysis, and it was necessary to build an environment with multiple IPs and multiple tools. Therefore, it was required to build an environment for each development project, it took time to start verification, and it was difficult to standardize the performance verification method.
- The system becomes more complex, and it is necessary to execute actual software on an FPGA or ASIC chip for performance analysis. But there was not an effective solution.
- It is required to perform the detailed analysis of performance defects that occur on the board using FPGA or ASIC, but it was impossible to get to know the detailed transfer status from the board. On the other hand, it takes long time to run simulation due to the large amount of data.
VARON AMBA solution
- Offers a flexibly configured on-chip verification IP and proprietary GUI that communicates with the verification IP
- Short time to generate a verification IP and start performance verification
- Easy and systematic analysis with rich portfolio of performance charts that visualize bus usage efficiency and responsiveness
- Supports all of simulation, emulation, FPGA, ASIC and ASSP
- No discrepancy between the verification results in simulation and in actual chips greatly reduces design backtracking.
- Supports AXI3, AXI4, ACE and APB
- Captures bus activity at transaction level
- Transaction-level detailed analysis for FPGA and ASIC
- Greatly reduces the amount of data and speeds display and data processing in simulation
Data transfer amount analysis
In addition to performance analysis based on total data transfer amount, VARON offers time-series transfer amount analysis for users to analyze the peak value of data transfer amount and the detailed data transfer status at that time even in FPGA and ASIC.
Since bus operating status is captured at transaction level, it is possible to analyze the latency status even in FPGA and ASIC, so it is also suitable to verify QoS control while actual application is running. VARON displays latency histogram, searches for transactions with latencies greater than user target value and highlights them.
Blog posted for example of investigating the cause of latency deterioration and verifying the results of countermeasures using VARON.