As the hardware comes together, software teams port their code and begin functional testing, along with timing analysis. Multiple cores and IP result in different teams accessing the hardware – often independently and then grouped together. Trouble can occur within one module and more often between modules with different clocks, latency, etc.
Having deep insight to the bus performance is a gift to software developers. Vtech’s VARON offers this insight for multiple clocks at the simulation, emulation, FPGA and even ASIC level with over 20 distinct charts and graphs.
For example, the peak value of data transfer and the detailed status of data transfer amount are gained by VARON’s time-series data transfer amount charts. The wait cycle, latency and data transfer time of each transaction are displayed on transaction timing charts which are cycle-accurately mapped. Software developers and system designers get to know in detail which bus master has a higher latency than expected and the performance degradation that has occurred in which data transfer cycle – all while the actual application is running.
Fig.1 Time-series Data Transfer Amount charts
Fig. 2 Transaction Timing Chart
We all know the scramble that occurs when a bug is found in the field. Preparing your ASIC with VARON allows the hardware and software teams to quickly identify performance issues and bottlenecks in corner cases uncovered in the field.
Save time and reduce risk with VARON insights.
“When the ASIC / SoC is completed and the actual software runs on it, the performance may not be as expected. With VARON IP inside the chip, engineers can bring up the design and have the insights they need on AMBA bus performance. VARON offers a seamless performance verification environment from simulation to real silicon, and I believe this tool greatly improves the verification methodology especially for FPGA and ASIC,” said Junichiro Minamitani, CTO of Verification Technology, Inc.
About VARON for FPGA and ASIC
- Consists of an on-chip monitor IP (VARON IP) and proprietary GUI
- Reconfigurable VARON IP per AMBA interconnect for clock frequency, data width, AMBA protocol and number of ports
- Offers rich performance charts including time-series data transfer amount and transaction timing charts.
- Support OS: Windows and Linux
- Support FPGA: Xilinx 7 series or later
- The GUI communicates with VARON IP via JTAG for FPGA and UART for ASIC. For FPGA the JTAG can be shared with Vivado.
Fig. 3 System configuration for FPGA