RISC-V core UVM verification

"In general, CPU core development requires many more man-hours for the verification phase than the design. This is because there are a huge number of items to be verified, such as the instruction sequences and the combination of exceptions and error occurrences. This blog introduces an example of RISC-V core UVM verification that Verification Technology USA, Inc. (Vtech) provided a startup company in the US as a service." released on May 26, 2021.


Customer challenges in achieving functional safety

"Various problems occur in the LSI development compliance with functional safety standards. This blog will describe 3 typical customer issues and the tips to address them." released on April 12, 2021.


Timing is everything: from punch lines to software development

"As the hardware comes together, software teams port their code and begin functional testing, along with timing analysis. Multiple cores and IP result in different teams accessing the hardware – often independently and then grouped together.  Trouble can occur within one module and more often between modules with different clocks, latency, etc." released on March 23, 2021.


Safety Concept in LSI development compliant with ISO26262

"The LSI development to achieve functional safety compliant with ISO26262 standard has three processes from Safety Concept to Design to Verification. This article describes the overview of Safety Concept, which is a unique process to the functional safety standard." released on February 15, 2021


VARON AMBA performance analysis demo

“Vtech introduces another VARON demo for SoC with arbitration method and 2 AXI interconnects. The bus master IPs with large amount of data transfers are connected to the main AXI.” released on December 14, 2020


VSTAR video processing demo

“Vtech introduces another VSTAR demo with video image processing. The image rotating algorithm is mapped to a Xilinx Kintex-7 FPGA K705 development board with a 300 MHz AXI stream and 200 MHz AXI bus.” updated on December 1, 2020


Effective Validation Method of Safety Mechanism Compliant with ISO 26262

“The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified value is not reached on the Fault Injection Simulation (using Gate Level) at the end of verification, it will cause iterations” released in Mentor Verification Horizon July 2020


Press Release

Vtech exhibiting EDA & FuSa solutions at DVCon U.S. 2021 - Virtual

"March 1 - 4, 2021; presenting EDA solutions for AMBA bus performance analysis and FPGA design auto-debugging, and functional safety and design services for LSI development; Scheduled Engagements – win Beats Solo Pro by Dr. Dre headphones"


Vtech introduced by Brian Bailey at Semiconductor Engineering

"It has been a long time since I was able to talk about a new verification company, but today I can introduce you to Verification Technology, or Vtech for short." released on July 15, 2020

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