New Generation EDA Tool

In verification of FPGA / ASIC designs that are getting larger and more complex, it is impossible to predict under what kind of situation we will encounter a failure and when it will occur. We offer efficient solutions to address unexpected or previously neglected problems and dramatically improve design verification productivity. Vtech has focused on LSI design verification since it was established in 2003. Our extensive expertise accumulated in third party LSI design verification services for diverse applications enables us to create unique solutions that make customer business much easier and more profitable.

VARON - AXI Performance Analyzer

In SoC (System on Chip), many IPs such as CPUs, its peripherals, GPUs, DSPs, and DDR controllers are integrated with subsystems via interconnects. The design is getting larger and more complex, and more and more interactions are taking place over the interconnects. Against this background, accurate performance analysis around the interconnect, efficient access to external memory, and optimization of its configuration are very important. Actually, the performance of external devices varies, and it's required to perform the same analysis under the condition that software is run on an actual chip. VARON is the only complete solution in the industry that offers easy-to-use performance analysis even for non-experts and high cost performance that can be used in any verification environment.

Performance analysis


Customer problems

  • Need Verification IP for simulation and emulation, plus rich debug tool
  • Learning how to use the Verification IPs and the debug tool is a big challenge
  • Don’t have expertise in performance analysis and don’t know where to start
  • Want to debug performance on FPGA or ASIC chip with running software, but major players do not offer
  • Slow to process large amount of data at signal level
  • Total cost of the tools and effort for performance analysis is high

VARON value proposition

  • A complete product with fully configurable on-chip Verification IP and proprietary GUI that communicates with the VIP
  • Easy to use with tool guided configuration of VIP for user requirements
  • Easy to debug with portfolio of rich performance charts and tool-tips
  • Support simulation, emulation, FPGA prototyping and system validation by ASIC/ASSP chip
  • Very fast with processing transaction level data dedicated for performance analysis
  • Low labor costs with short time to implement

VARON advantages

  • Cover the entire process of LSI design verification
  • Fully configurable on-chip VIP dedicated for performance analysis
    • Monitor AXI interconnects at transaction level for data transfer amount and wait, burst length and latency of each transaction
    • Flexibly configured by user requirements for port configuration and verification environment, and automatically implemented to user design
    • Independently configured by port with IDs association across interconnects
  • Tool guided performance analysis for ease of use
    • Quick start with processing transaction level data
    • Portfolio of rich performance charts
      • 10 types of charts for read/write and 20 charts per port group
    • Tool-tips showing the detailed data of interest to the mouse point
    • Find Out-of-Range to highlight data out of expectation

Latency distribution

Transaction timing chart

VSTAR - FPGA Bug Auto-Analyzer

As FPGAs become larger and larger, their designs are becoming increasingly complex, with newly developed subsystems, as well as a wide variety of IP provided by FPGA vendors and third parties, integrated into the design. Debugging is a more challenging task. Traditional solutions do not allow immediate debugging when unexpected problems occur, so trigger conditions must be set, and the FPGA must be re-P&R and re-executed for debugging. In the first place, it’s difficult to find debugging conditions for problems that are not intended by the designer. Especially for large-scale FPGAs, it’s not unusual for several iterations of debugging to take several weeks to solve the problem. VSTAR is the only solution in the industry that eliminates the need for user-defined trigger conditions and enables immediate debugging of problems that occur over many days of continuous operation.

Traditional use case


Problems in traditional solution

  • Can not debug immediately after failures that happened to be found
  • Need user defined trigger condition for the detailed debug on waveform
  • Time-consuming for multiple iterations of FPGA execution and P&R that can take over a day with large FPGAs
  • Difficult in finding appropriate debug condition for unexpected or unintended design problems

VSTAR value proposition

  • Immediate debug after failures detected at system level even in lengthy consecutive run
  • No need for user defined trigger conditions by auto-generated design rules
  • Quick start with narrowing down from auto-detected errors at system level to the detailed debug on waveform
  • Easy of debug based on design specification or designer expectation
  • Diagnostics in mass production for fail safe

VSTAR use case

VSTAR features

  • Tool guided VIP configuration on Design Window
    • Multi-group signals for design rules and waveforms
    • Auto-implementation onto user design
  • Auto-generation of design rules
    • Probe multi-grouped signals at the same time
    • Capture states transition and timing intervals, and extract design rules by group
    • The rules to be saved to file as reference
    • User defined rules for early stage of verification
  • Auto-detection of errors
    • Detect mismatches with design rules as triggers and stop capturing waveform
    • Display sequences and highlight auto-detected errors on Debug Window
    • Output VCD on GTKWave for the detailed debug

System configuration