New Generation EDA Tool

In verification of FPGA / ASIC designs that are getting larger and more complex, it is impossible to predict under what kind of situation we will encounter a failure and when it will occur. We offer efficient solutions for unexpected or previously neglected problems to dramatically improve design verification productivity. Vtech has focused on LSI design verification since it was established in 2003. Our extensive expertise accumulated in third party LSI design verification services for diverse applications enables us to create unique solutions that make customer business much easier and more profitable.


VARON - AXI Performance Analyzer

Customer problems

  • Need Verification IP for simulation and emulation, plus rich debug tool
  • Learning how to use the Verification IPs and the debug tool is a big challenge
  • Don’t have expertise in performance analysis and don’t know where to start
  • Want to debug performance on FPGA or ASIC chip with running software, but major players do not offer
  • Slow to process large amount of data at signal level
  • Total cost of the tools and effort for performance analysis is high

VARON value proposition

  • A complete product with fully configurable on-chip Verification IP and proprietary GUI that communicates with the VIP
  • Easy to use with tool guided configuration of VIP and performance analysis with portfolio of rich charts and tool-tips
  • Support simulation, emulation, FPGA prototyping and system validation by ASIC/ASSP chip
  • Very fast with processing transaction level data dedicated for performance analysis
  • Low labor costs with short time to implement

VARON advantages

  • Cover the entire process of LSI design verification
  • Fully configurable on-chip VIP dedicated for performance analysis
    • Monitor AXI at transaction level for data transfer amount, burst length and latency
    • Flexibly configured for user needs and automatically implemented to user design
    • Independently configured by port group with IDs association across interconnects
  • Tool guided performance analysis for ease of use
    • Quick start with processing transaction level data
    • Portfolio of rich performance charts
      • 10 types of charts for each read and write
      • 20 charts per port group
    • Tool-tips showing the detailed data of interest to the mouse point
    • Find Out-of-Range to highlight data out of expectation

Latency distribution

Transaction timing chart


VSTAR - FPGA Bug Auto-Analyzer

Traditional use case

Fundamental problems

  • Can not debug immediately after failures that happened to be found
  • Need user defined trigger condition for the detailed debug on waveform
  • Time-consuming for multiple iterations of re-execution and P&R that can take over a day with large FPGAs
  • Difficult in finding appropriate debug condition for unexpected or unintended design problems

VSTAR advantages

  • Immediate debug after failures at system level
  • No need for user defined trigger conditions
  • Quick start to narrow down from auto-detected errors at system level to the detailed debug on waveform
  • Easy of debug based on design specification or designer expectation
  • Diagnostics in mass production for fail safe

VSTAR use case

VSTAR features

  • JTAG communication between on-chip VIP and GUI
  • Tool guided VIP configuration on Design Window
    • Multi-group signals for design rules and waveforms
    • Auto-implementation onto user design
  • Auto-generation of design rules
    • Probe multi-grouped signals at the same time
    • Capture states transition and timing intervals, and extract design rules by group
    • The rules to be saved to file as reference
    • User defined rules for early stage of verification
  • Auto-detection of errors
    • Detect mismatches with design rules as triggers and stop capturing waveform
    • Display sequences and highlight auto-detected errors on Debug Window
    • Output VCD on GTKWave for the detailed debug

System configuration