Front-end Design and Verification Services

Vtech offers LSI front-end design services with third-party verification as its core technology. We have rich experience in Verilog, VHDL and SystemVerilog designs, and high skill in dynamic, static, formal, random and UVM verifications. We have also accumulated application specific expertise for the advanced systems such as CMOS image sensor, medical equipment, factory automation, automotive ECU, communication device, edge computing and SSD.

Features
  • Expert level in verification languages such as UVM and SystemVerilog
  • Expert level with developing UVM-based SystemVerilog testbenches
  • Deep expertise in RISC-V core verification with UVM and in-house developed ISS (C model)
  • Deep experience in property verification with formal tools
  • Strong and relevant expertise with ASIC simulation tools and advanced verification method
  • Deep experience with writing block-level and SoC test-plans
  • RTL design with consideration for ease of verification
  • High customer appreciation to the quality of design documents
  • Skilled in developing test software required for CPU built-in SoC verification, and designing SoC type FPGA
  • Full-scale embedded software development, and board design jointly with partners
  • EDA solutions, plus Design Services
    • VARON: AMBA bus performance optimization and reporting, support for customer proprietary bus protocol
    • VSTAR: FPGA design defects debugging and reporting, real-time error monitoring for customer equipment in the field
Engagement models
  1. Onsite project based:

Option 1:  Design and verification of a block – own the design and the verification

Option 2: Provide third-party verification of a block including random verification

Option 3: Complete chip top-down build and the connectivity verification

* Work with designers, create test plans, implement in UVM, run and complete tests.

  1. Hybrid project based, consisting of:
  • A bridge engineer working onsite as a customer team member to liaison with offshore members for design and verification tasks
  • Several offshore members in charge of the design and verification tasks in Japan
  1. Full remote, Offshore to Japan, featured by:
  • We have many engineers who have more than 20 years of design experience in Japanese semiconductor manufacturers.
  • We provide design services with Japanese quality.
Tools experience
  • Synopsys: VCS®; Verdi®; Z01X™
  • Cadence: Incisive®; Xcelium™; JasperGold®; Palladium®; Verification IPs
  • Mentor: Questa®
  • Xilinx: Vivado®
  • Intel: Quartus®

Scope of Work

  • FPGA: Specification creation, RTL coding & verification, implementation and on-system verification
  • ASIC: Specification creation, RTL coding & verification, logic synthesis and chip verification

Track Record