Meeting Timelines with On-Demand Design Services

 

"Often companies are fighting timelines to complete RTL or verification.  And, identifying and hiring talent these days is a long process, and expensive. Vtech has been delivering On-Demand Design Services since 2003 and has completed over 250 projects."

Released on September 7, 2021. Learn more

RISC-V core UVM verification

"In general, CPU core development requires many more man-hours for the verification phase than the design. This is because there are a huge number of items to be verified, such as the instruction sequences and the combination of exceptions and error occurrences. This blog introduces an example of RISC-V core UVM verification that Verification Technology USA, Inc. (Vtech) provided a startup company in the US as a service."

Released on May 26, 2021. Learn more

Customer challenges in achieving functional safety

"Various problems occur in the LSI development compliance with functional safety standards. This blog will describe 3 typical customer issues and the tips to address them."

Released on April 12, 2021. Learn more

"As the hardware comes together, software teams port their code and begin functional testing, along with timing analysis. Multiple cores and IP result in different teams accessing the hardware – often independently and then grouped together.  Trouble can occur within one module and more often between modules with different clocks, latency, etc."

Released on March 23, 2021. Learn more

"The LSI development to achieve functional safety compliant with ISO26262 standard has three processes from Safety Concept to Design to Verification. This article describes the overview of Safety Concept, which is a unique process to the functional safety standard."

Released on February 15, 2021. Learn more

“Vtech introduces another VARON demo for SoC with arbitration method and 2 AXI interconnects. The bus master IPs with large amount of data transfers are connected to the main AXI.”

Released on December 14, 2020. Learn more

“Vtech introduces another VSTAR demo with video image processing. The image rotating algorithm is mapped to a Xilinx Kintex-7 FPGA K705 development board with a 300 MHz AXI stream and 200 MHz AXI bus.”

Updated on December 1, 2020. Learn more

“The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified value is not reached on the Fault Injection Simulation (using Gate Level) at the end of verification, it will cause iterations”

Released in Mentor Verification Horizon July 2020. Learn more