A single reconfigurable monitor IP and proprietary GUI offering quick and systematic analysis with rich performance charts to visualize bus usage efficiency and responsiveness on simulation, emulation, FPGA and ASIC
AMBA Performance Analyzer
The only complete solution in the industry for AMBA transaction performance analysis with configurable on-chip Verification IP and proprietary GUI. Quick and systematic analysis with rich portfolio of performance charts and tool-tips to visualize bus usage efficiency and responsiveness. Little or less speed degradation with any platform – simulator, hardware emulator, FPGA device and ASIC chip. Short time to transaction performance analysis in a few minutes.
FPGA Design Auto-Debugger
The industry’s only solution for FPGA design auto-debug with configurable on-chip Verification IP and proprietary GUI. Auto-generates rules for the signal state transitions in real time with the patent-applied technology to eliminate the need for user defined trigger conditions and free users from multiple iterations of FPGA P&R and execution. Easy to debug with narrowing down from auto-detected errors at system level to the detailed debug on waveform. Displays system level operation up to 100,000x longer than waveform.
Functional Safety Services
The only independent company in the world with track record for LSI development to cover the entire functional safety flow from safety concept to design and verification. Accumulating expertise and knowhow in over 1,000 projects for various types of applications, pursing state-of-the-art verification technologies. Led by Functional Safety Managers (FSM) and Functional Safety Engineers (FSE) qualified for ISO26262 and IEC61508, who have rich experience in LSI design and verification.
“In general, CPU core development requires many more man-hours for the verification phase than the design. This is because there are a huge number of items to be verified, such as the instruction sequences and the combination of exceptions and error occurrences. This blog introduces an example of RISC-V core UVM verification that Verification Technology USA, Inc. (Vtech) provided a startup company in the US as a service.” released on May 26, 2021.
“Various problems occur in the LSI development compliance with functional safety standards. This blog will describe 3 typical customer issues and the tips to address them.” released on April 12, 2021.
“As the hardware comes together, software teams port their code and begin functional testing, along with timing analysis. Multiple cores and IP result in different teams accessing the hardware – often independently and then grouped together. Trouble can occur within one module and more often between modules with different clocks, latency, etc.”
“March 1 – 4, 2021; presenting EDA solutions for AMBA bus performance analysis and FPGA design auto-debugging, and functional safety and design services for LSI development; Scheduled Engagements – win Beats Solo Pro by Dr. Dre headphones”
“The LSI development to achieve functional safety compliant with ISO26262 standard has three processes from Safety Concept to Design to Verification. This article describes the overview of Safety Concept, which is a unique process to the functional safety standard.”
“Vtech introduces another VARON demo for SoC with arbitration method and 2 AXI interconnects. The bus master IPs with large amount of data transfers are connected to the main AXI.”
“Vtech introduces another VSTAR demo with video image processing. The image rotating algorithm is mapped to a Xilinx Kintex-7 FPGA K705 development board with a 300 MHz AXI stream and 200 MHz AXI bus.”