AXI Performance Analyzer

Utilized in the entire process of LSI development by software on-chip verification IP and hardware’s. GUI software compiles transaction level data captured by the on-chip IP, analyzes and displays 14 kinds of chart for quick and systematic analysis.

FPGA Bug Analyzer

Based on Xilinx technology and automatically detect corner cases even in lengthy consecutive run and output VCD on waveform viewer to help user debug. No need of setting trigger condition frees user from useless trials and errors to catch design bug.

Functional Safety Solution

Based on our extensive experience in third party LSI design verification for various types of application. We have 7 FSEs qualified as functional safety practitioners and offer service that visualizes risks for our customers to deliver low cost and high quality LSIs requested by end users.

Vtech Platinum Sponsoring XDF

North America: October 1 & 2, Fairmont San Jose (USA)
EMEA: November 12 & 13, World Forum, The Hague (Netherlands)
Asia: December 3 & 4, National Convention Center, Beijing (China)

Demonstrate VARON and VSTAR consisting of on-chip verification IP developed in-house and proprietary GUI software.

  • Present the product’s system configuration and advantages, followed by design flow demonstration using GUI software.
  • VARON software displays charts for data transfer amount, bus transactions, and latency distribution. The demo DUT consisting of 8 bus masters and 2 bus slaves is connected to software verification IP via DPI-C and operated by software simulator.
  • VSTAR software displays the entire signals sequences with auto-detected errors and outputs VCD for waveform observation. The demo DUT and hardware verification IP are implemented into Xilinx UltraScale+ FPGA for real operation.

Present functional safety support for Xilinx FPGAs.

  • Utilization of “Xilinx Safety Manual” in safety analysis
  • FPGA development method using Xilinx Safety Lounge utility