AXI Performance Analyzer

The only complete solution in the industry with configurable on-chip Verification IP and proprietary GUI.

Can be utilized in the entire process of LSI development with support for simulator, HW emulator, FPGA and ASIC chip.

Easy to use with the tool guided configuration of the VIP and performance analysis on the GUI offering portfolio of rich performance charts and tool-tips.

FPGA Bug Auto-Analyzer

The only one solution in the industry with configurable on-chip Verification IP and proprietary GUI.

Automatically generates design rules and eliminates the need for user defined trigger conditions to free users from multiple iterations of FPGA P&R and run.

Easy to debug with narrowing down from auto-detected errors at system level to the detailed debug on waveform.

Functional Safety Solution

The only one solution for LSI in the industry.

Based on our successful experience in 1,300 third party LSI design verification projects for various types of application.

We have 16 FSEs qualified as functional safety practitioners and offer service that visualizes risks for our customers to deliver low cost and high quality LSIs requested by end users.

Vtech Exhibiting at DVCon US 2020

Design and Verification Conference at DoubleTree Hotel, San Jose, CA

  • Booth # 1005 on March 2 – 4, 2020
  • Demonstrate EDA solutions for AXI performance analysis and FPGA bug analysis with auto design rule generation

Vtech USA Raffle at DVCon 2020 – Apple AirPods Pro

“Congratulations to Mark at MathWorks for winning the Vtech USA: DVCon 2020 raffle.  Mark received Apple AirPods Pro as a prize.

We thank everyone who stopped by our booth to learn more about VARON (AXI performance analysis) and VSTAR (FPGA debug with auto generation of design rules) and entering our raffle drawing.

Vtech USA team”

Vtech Platinum Sponsoring XDF

North America: October 1 & 2, Fairmont San Jose (USA)
EMEA: November 12 & 13, World Forum, The Hague (Netherlands)
Asia: December 3 & 4, National Convention Center, Beijing (China)

Demonstrate VARON and VSTAR consisting of on-chip verification IP developed in-house and proprietary GUI software.

  • Present the product’s system configuration and advantages, followed by design flow demonstration using GUI software.
  • VARON software displays charts for data transfer amount, bus transactions, and latency distribution. The demo DUT consisting of 8 bus masters and 2 bus slaves is connected to software verification IP via DPI-C and operated by software simulator.
  • VSTAR software displays the entire signals sequences with auto-detected errors and outputs VCD for waveform observation. The demo DUT and hardware verification IP are implemented into Xilinx UltraScale+ FPGA for real operation.

Present functional safety support for Xilinx FPGAs.

  • Utilization of “Xilinx Safety Manual” in safety analysis
  • FPGA development method using Xilinx Safety Lounge utility